The future of high performance computing is geared toward packing as much performance capability as possible into the smallest real estate as possible. More cores are being added to chips, more chips per computing module, more software execution threads per core, etc. All of this amounts to shifting performance barriers and more “congestion”. As more cores per socket are added, each with 2 to 4 more logical threads, the challenge becomes keeping the system balanced. One side effect of an unbalanced system is that bus traffic will increase, and at peak usage, may saturate the system bus completely. The outcome will be a system bottlenecked on bus traffic, with underutilized CPU, memory, and I/O resources. The computing power of the machine will become limited by the size of the bus.
Some systems have attempted to moderate information traffic on a saturated system bus proactively based on weights supplied at some start-up point. Such systems however, may induce a lot more bus traffic because it must sample continually to maintain the weights and moderate the traffic, not to mention new bus requesters will mean re-evaluating everyone's weights. There is a lot of calculating and re-calculating and bus requesters must know what their bandwidth requirements are ahead of time. Such prior art applications have to rely on everyone else knowing their requirements to make the system work, and that is unlikely.
Thus, there is a need to provide a bus access moderation system which is passive and avoids the need to calculate and re-calculate bandwidth distribution among bandwidth requesting devices.